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Integrated Circuit Systems, Inc.
Product Data Sheet
M2040
FIN_SEL1 GND AUTO DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC 27 26 25 24 23 22 21 20 19
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
PIN ASSIGNMENT (9 x 9 mm SMT)
GENERAL DESCRIPTION
The M2040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in fault tolerant computing applications. It features dual differential inputs with two modes of input selection: manual and automatic upon clock failure. The clock multiplication ratios and output divider ratio are pin selectable. External loop components allow the tailoring of PLL loop response.
FEATURES
Integrated SAW (surface acoustic wave) delay line; VCSO frequency of 400.00 or 533.3334 MHz;* outputs VCSO frequency or half; pin-configurable dividers Loss of Lock (LOL) indicator output Narrow Bandwidth control input (NBW Pin); Initialization (INIT) input overrides NBW at power-up Dual reference clock inputs support LVDS, LVPECL, LVCMOS, LVTTL Automatic (non-revertive) reference clock reselection upon clock failure; controlled PLL slew rate ensures normal system operation during reference reselection Acknowledge pin indicates the actively selected reference input Dual differential LVPECL outputs Low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz) Industrial temperature available Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package
FIN_SEL0 MR_SEL REF_ACK LOL NBW VCC DNC DNC DNC
28 29 30 31 32 33 34 35 36
M2040
(Top View)
18 17 16 15 14 13 12 11 10
P_SEL INIT nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND
Figure 1: Pin Assignment
Example Input / Output Frequency Combinations
Input (MHz) VCSO * (MHz) 200.0000 400.0000 213.3333 266.6667 533.3334 284.4444 Output (MHz) 200.0000 400.0000 266.6667 533.3334
Table 1: Example Input / Output Frequency Combinations
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
Loop Filter
M2040
NBW
MUX PLL Phase Detector
DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_ACK REF_SEL AUTO Auto INIT LOL MR_SEL FIN_SEL1:0 P_SEL
2
Ref Sel
0
R Div VCSO
1
0 1
M Div
LOL Phase Detector
Mfin Divider
GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN
1 2 3 4 5 6 7 8 9
FOUT0 nFOUT0
M / R Divider
P Divider
Mfin Divider
LUT LUT
FOUT1 nFOUT1
Figure 2: Simplified Block Diagram
M2040 Datasheet Rev 1.0
M2040 Frequency Translation PLL with AutoSwitch
Revised 28Jan2005
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Networking & Communications
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M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
Product Data Sheet
PIN DESCRIPTIONS
Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 11, 19, 33 12 13 15 16 17 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC VCC FOUT1 nFOUT1 FOUT0 nFOUT0 INIT I/O Configuration Description
Ground Input Output Input Power Output Output Input No internal terminator No internal terminator Internal pull-UP resistor1 Internal pull-down1 Biased to Vcc/2 2 Input Internal pull-down resistor1 Input Internal pull-down resistor1 Biased to Vcc/2 2 Input Internal pull-down resistor1 Input Input Input Internal pull-down resistor1 Internal pull-UP resistor1 Internal pull-UP resistor1
Power supply ground connections. External loop filter connections. See Figure 5, External Loop Filter, on pg. 7.
Power supply connection, connect to +3.3V. Clock output pair 1. Differential LVPECL. Clock output pair 0. Differential LVPECL. Power-on Initialization; LVCMOS/LVTTL: Logic 1 allows device to enter narrow mode if selected (in addition must have 8 LOL=0 counts) Logic 0 forced device into wide bandwidth mode. Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 5, P Divider Selector Values and Frequencies, on pg. 3. Reference Differential LVPECL/ LVDS clock input Differential LVPECL/ LVDS, or single pair 1. ended LVCMOS/ LVTTL Reference clock input selection. LVCMOS/LVTTL. Logic 1 selects DIF_REF1/nDIF_REF1 inputs Logic 0 selects DIF_REF0/nDIF_REF0 inputs Reference Differential LVPECL/ LVDS clock input Differential LVPECL/ LVDS, or single pair 0. ended LVCMOS/ LVTTL Automatic/manual reselection mode for clock input: Logic 1 automatic reselection upon clock failure (non-revertive) Logic 0 manual selection only (using REF_SEL) Input clock frequency selection. LVCMOS/LVTTL. (For FIN_SEL1:0, see Table 3 on pg. 3.) M & R PLL divider ratio selection. LVCMOS/ LVTTL. (For MR_SEL, see Table 4 on pg. 3.) Reference Acknowledgement pin for input mux state; outputs the currently selected reference input pair: Logic 1 indicates nDIF_REF1, DIF_REF1 Logic 0 indicates nDIF_REF0, DIF_REF0 Loss of Lock indicator output. 3 Logic 1 indicates loss of lock. Logic 0 indicates locked condition. Narrow Bandwidth enable. LVCMOS/LVTTL: Logic 1 - Narrow loop bandwidth, RIN = 2100k . . Logic 0 - Wide (normal) bandwidth, RIN = 100k Do Not Connect.
Table 2: Pin Descriptions
18 20 21 22 23 24
P_SEL nDIF_REF1 DIF_REF1 REF_SEL nDIF_REF0 DIF_REF0
25 27 28 29
AUTO FIN_SEL1 FIN_SEL0 MR_SEL
30
REF_ACK
Output
31
LOL
Output Internal pull-UP resistor1
32 34, 35, 36
NBW DNC
Input
Note 1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 8. Note 2: Biased to Vcc/2, with 50k to Vcc and 50k to ground. Float if using DIF_REF1 as LVCMOS input. See DC Characteristics on pg. 8. Note 3: See LVCMOS Outputs in DC Characteristics on pg. 8.
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M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
Product Data Sheet
DETAILED BLOCK DIAGRAM
R LOOP C LOOP R POST C POST C POST R LOOP C LOOP OP_OUT R POST nOP_OUT nVC VC
External Loop Filter Components
M2040
OP_IN
nOP_IN
NBW
MUX PLL Phase Detector
DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_ACK REF_SEL AUTO Auto INIT LOL MR_SEL FIN_SEL1:0 P_SEL
2
Ref Sel
R IN
0
R
Divider R IN Loop Filter Amplifier
1
Phase Locked Loop (PLL)
SAW Delay Line
Phase Shifter
VCSO
M
0 1
LOL Phase Detector
Divider
Mfin Divider
FOUT0 nFOUT0
M / R Divider
P Divider FOUT1 nFOUT1
Mfin Divider
LUT LUT
Figure 3: Detailed Block Diagram
PLL DIVIDER SELECTION TABLES
Mfin (Frequency Input) Divider Look-Up Table (LUT) The FIN_SEL1:0 pins select the feedback divider value ("Mfin").
FIN_SEL1:0
Post-PLL Divider The M2040 also features a post-PLL (P) divider for the output clocks. It divides the VCSO frequency to produce one of two selectable output frequencies (1/2 or 1/1 of the VCSO frequency). That selected frequency appears on both clock output pairs. The P_SEL pin selects the value for the P divider.
Example: M2040-533.3334
1 1 0 0
1 0 1 0
Mfin Value 1 4 8 32
Table 3: Mfin (Frequency Input) Divider Look-Up Table (LUT)
P_SEL
P Value 2 1
M / R Divider Ratio Look-up Table (LUT) The MR_SEL pin selects the feedback and reference divider values M and R, respectively.
MR_SEL M R
1 0
Output Frequency (MHz) 266.6667 533.3334
Table 5: P Divider Selector Values and Frequencies
Description
0 1
Used when Fin = 32/16 = 1/2 Fvcso 32 16 (e.g., Fin=266.6667MHz, Fvcso= 533.3334MHz1) Used when Fin = 30/16 = 0.53334 Fvcso 30 16 (e.g., Fin=284.444MHz, Fvcso= 533.3334 MHz 1)
Table 4: M / R Divider Ratio Look-up Table (LUT)
Note 1: Fvcso= Example 533.3334MHz in M2040-01-533.3334.
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M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
Product Data Sheet Input Reference Clocks Two clock reference inputs and a selection mux are provided. Either reference clock input can accept a differential clock signal (such as LVPECL or LVDS) or a single-ended clock input (LVCMOS or LVTTL on the non-inverting input).
A single-ended reference clock on the unselected reference input can cause an increase in output clock jitter. For this reason, differential reference inputs are preferred; interference from a differential input on the non-selected input is minimal.
FUNCTIONAL DESCRIPTION
The M2040 is a PLL (Phase Locked Loop) based clock generator that generates two output clocks synchronized to one of two selectable input reference clocks. An internal high "Q" SAW delay line provides a low jitter clock output. The device is pin-configured for feedback divider and output divider values. Output is LVPECL compatible. External loop filter component values set the PLL bandwidth to optimize jitter attenuation characteristics. The device features dual differential inputs with two input selection modes: manual and automatic upon clock failure. (The differential inputs are internally configured for easy single-ended operation.) The M2040 includes: a Loss of Lock (LOL) indicator, a reference mux state acknowledge pin (REF_ACK), a Narrow Bandwidth control input pin (NBW pin), and a Power-on Initialization (INIT) input (which overrides NBW=0 to facilitate acquisition of phase lock). Hitless Switching (HS) is an optional feature that provides a controlled output clock phase change during a reference clock reselection. HS is triggered by a Loss of Lock detection by the PLL.
Configuration of a single-ended input has been facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2, with 50k to Vcc and 50k to ground. The input clock structure, and how it is used with either LVCMOS/LVTTL inputs or a DC- coupled LVPECL clock, is shown in Figure 4.
DIF_REF0
50k VCC 50k X 50k MUX
LVCMOS/ LVTTL
nDIF_REF0
VCC
127
0
DIF_REF1
LVPECL
1
82
VCC 127
50k
VCC 50k
nDIF_REF1 REF_SEL
82
50k
Figure 4: Input Reference Clocks
Differential Inputs
Differential LVPECL inputs are connected to both reference input pins in the usual manner. The external load termination resistors shown in Figure 4 (the 127 and 82 resistors) is ideally suited for both AC and DC coupled LVPECL reference clock lines. These provide the 50 load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are connected to the non-inverting reference input pin (DIF_REF0 or DIF_REF1). The inverting reference input pin (nDIF_REF0 or nDIF_REF1) must be left unconnected.
In single-ended operation, when the unused inverting input pin (nDIF_REF0 or nDEF_REF1) is left floating (not connected), the input will self-bias at VCC/2.
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PLL Operation The M2040 is a complete clock PLL. It uses a phase detector and configurable dividers to synchronize the output of the VCSO with the selected reference clock. The "M" divider (and the "Mfin" divider) divides the VCSO output frequency, feeding the result into the plus input of the phase detector.
The frequency input ("Mfin") divider gives the device the capability to be adapted for use with other input frequencies.
M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
Product Data Sheet Loss of Lock Indicator Output Pin Under normal device operation, when the PLL is locked, LOL remains at logic 0. Under circumstances when the VCSO cannot lock to the input (as measured by a greater than 4 ns discrepancy between the feedback and reference clock rising edges at the phase detector) the LOL output goes to logic 1. The LOL pin will return back to logic 0 when the phase detector error is less than 2 ns. The loss of lock indicator is a low current CMOS output. Narrow Loop Bandwidth Control Pin (NBW Pin) A Narrow Loop Bandwidth control pin (NBW pin) is included to adjust the PLL loop bandwidth. In normal (wide) bandwidth mode (NBW=0), the internal resistor Rin is 100k . With the NBW pin asserted, the internal resistor Rin is changed to 2100k. This lowers the loop bandwidth by a factor of about 21 (2100 / 100) and lowers the damping factor by about 4.6 (the square root of 21), assuming the same loop filter components.
The output of the "R" divider is fed into the minus input of the phase detector. The phase detector compares its two inputs. The phase detector output, filtered externally, causes the VCSO to increase or decrease in frequency as needed to phase- and frequency-lock the VCSO to the reference input.
The value of M plus Mfin directly affects closed loop bandwidth.
The relationship between the nominal VCSO center frequency (Fvcso), the M divider, and the input reference frequency (Fref_clk) is: Fvcso = Fref_clk x ------------------------The M, R, and Mfin dividers can be set by pin configuration using the input pins MR_SEL, FIN_SEL1, and
FIN_SEL0. M x Mfin R
P Divider and Outputs The M2040 provides two differential LVPECL output pairs: FOUT0 and FOUT1. One output divider (the "P" divider) is used for both the FOUT0 and FOUT1 output pairs. By using the P divider, the output frequency can be the VCSO frequency (Fvcso) or 1/2 Fvcso. The P_SEL pin selects the value for the P divider: logic 1 sets P to divide-by-2, logic 0 sets P to divide-by-1.
See Table 5, P Divider Selector Values and Frequencies, on pg. 3.
When the P divider is included, the complete relationship for the output frequency (Fout) is defined as: M x Mfin Fvcso Fout = ------------------- = Fref_clk x ------------------------P Rx P
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Automatic Reference Clock Reselection This device offers an automatic reference clock reselection feature for switching input reference clocks upon a reference clock failure. With the AUTO input pin set to high and the LOL output low, the device is placed into automatic reselection (AutoSwitch) mode. Once in AutoSwitch mode, when LOL then goes high (due to a reference clock fault), the input clock reference is automatically reselected internally, as indicated by the state change of the REF_ACK output. Automatic clock reselection is made only once (it is non-revertive). Re-arming of automatic mode requires placing the device into manual selection (Manual Select) mode (AUTO pin low) before returning to AutoSwitch mode (AUTO pin high).
Using the AutoSwitch Feature See also Table 6, Example AutoSwitch Sequence.
M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
Product Data Sheet Once a reference fault occurs, the LOL output goes high and the input reference is automatically reselected. The REF_ACK output always indicates the reference selection status and the LOL output always indicates the PLL lock status. A successful automatic reselection is indicated by a change of state of the REF_ACK output and a momentary level high of the LOL output (minimum high time is 10ns).
If an automatic reselection is made to a non-valid reference clock (one to which the PLL cannot lock), the REF_ACK output will change state but the LOL output will remain high.
No further automatic reselection is made; only one reselection is made each time the AutoSwitch mode is armed. AutoSwitch mode is re-armed by placing the device into Manual Select mode (AUTO pin low) and then into AutoSwitch mode again (AUTO pin high). Following an automatic reselection and prior to selecting Manual Select mode (AUTO pin low), the REF_SEL pin has no control of reference selection. To prevent an unintential reference reselection, AutoSwitch mode must not be re-enabled until the desired state of the REF_SEL pin is set and the LOL output is low. It is recommended to delay the re-arming of AutoSwitch mode, following an automatic reselection, to ensure the PLL is fully locked on the new reference. In most system configurations, where loop bandwidth is in the range of 100-1000 Hz and damping factor below 10, a delay of 500 ms should be sufficient. Until the PLL is fully locked intermittent LOL pulses may occur.
In application, the system is powered up with the device in Manual Select mode (AUTO pin is set low), allowing sufficient time for the reference clock and device PLL to settle. The REF_SEL input selects the reference clock to be used in Manual Select mode and the initial reference clock used in AutoSwitch mode. The REF_SEL input state must be maintained when switching to AutoSwitch mode (AUTO pin high) and must still be maintained until a reference fault occurs.
Example AutoSwitch Sequence
0 = Low; 1 = High. Example with REF_SEL initially set to 0 (i.e., DIF_REF0 selected)
REF_SEL Selected REF_ACK AUTO LOL Conditions
Input
Clock Input DIF_REF0 DIF_REF0 DIF_REF0
Output
Input
Output
Initialization
0 0 0 0 0 0 0 -11 1
0 0 0 0 0 -11 1 1 1
0 0 -11 1 1 1 1 -0-1-
1 -00 0 -11 -00 0 0
Device power-up. Manual Select mode. DIF_REF0 input selected reference, not yet locked to.
LOL to 0: Device locked to reference (may get intermittent LOL pulses until fully locked). AUTO set to 1: Device placed in AutoSwitch mode (with DIF_REF0 as initial reference clock).
Operation & Activation
DIF_REF0 DIF_REF0 -DIF_REF1DIF_REF1 DIF_REF1 DIF_REF1 DIF_REF1
Normal operation with AutoSwitch mode armed, with DIF_REF0 as initial reference clock.
LOL to 1: Clock fault on DIF_REF0, loss of lock indicated by LOL pin, ... ... and immediate automatic reselection to DIF_REF1 (indicated by REF_ACK pin). LOL to 0: Device locks to DIF_REF1 (assuming valid clock on DIF_REF1).
Re-initialization
REF_SEL set to 1: Prepares for Manual Selection of DIF_REF1 before then re-arming AutoSwitch. AUTO set to 0: Manual Select mode entered briefly, manually selecting DIF_REF1 as reference. AUTO set to 1: Device is placed in AutoSwitch mode (delay recommended to ensure device fully locked), re-initializing AutoSwitch with DIF_REF1 now specified as the initial reference clock.
Table 6: Example AutoSwitch Sequence
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Hitless Switching Option Hitless Switching is a device option that can be specified at time of order. (Please contact ICS.) The M2040-01 remains in wide bandwidth mode if NBW = 0. When NBW = 0, placing the device into wide bandwidth operation, the optional Hitless Switching (HS) function will automatically place the device into narrow bandwidth operation during reference reselection. This provides a controlled output clock phase change while the PLL is acquiring phase lock to a new reference clock phase. The HS function is trigged by a loss of lock event. Wide bandwidth is resumed once the PLL relocks to the input reference. (When the NBW pin = 1, the device operates in narrow bandwidth continually and hence the HS mode does not apply). The HS function is armed after the device locks to the input clock reference (8 successive phase detector clock cycles with LOL low). Once armed, HS is triggered by detection at the phase detector of a single phase error greater than 4 ns (rising edges). Once triggered, the HS function narrows the loop bandwidth until the PLL is locked to the selected reference (8 successive phase detector clock cycles with LOL low). When pin AUTO = 1 (automatic reference reselection mode) HS is used in conjunction with input reselection. When AUTO = 0 (manual mode), HS will still occur upon an input phase transient, however the clock input is not reselected (this enables hitless switching when using an external MUX for clock selection). Power-Up Initialization Function (INIT Pin) The initialization function provides a short-term override of the narrow bandwidth mode when the device is powered up in order to facilitate phase locking. When INIT is set to logic 1, initialization is enabled. With NBW set to logic 1 (narrow bandwidth mode), the initialization function puts the PLL into wide bandwidth mode until eight consecutive phase detector cycles External Loop Filter Component Values 1
M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
Product Data Sheet occur without a single LOL event. Once the eight valid PLL locked states have occurred, the PLL bandwidth is automatically reduced to narrow bandwidth mode. When INIT is logic 0, the device is forced into wide bandwidth mode unconditionally. External Loop Filter The M2040 requires the use of an external loop filter components. These are connected to the provided filter pins (see Figure 5). Because of the differential signal path design, the implementation consists of two identical complementary RC filters as shown in Figure 5, below.
RLOOP CLOOP RPOST CPOST CPOST RLOOP OP_IN
4 9
CLOOP OP_OUT
8 5
RPOST nOP_OUT nVC
6 7
nOP_IN
VC
Figure 5: External Loop Filter
PLL bandwidth is affected by the total "M" (feedback divider) value, loop filter component values, and other device parameters. See Table 7, External Loop Filter Component Values, below. PLL Simulator Tool Available A free PC software utility is available on the ICS website (www.icst.com). The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application.
VCSO Parameters: KVCO = 800kHz/V, VCO Bandwidth = 700kHz. See AC Characteristics on pg. 9 for PLL Loop Constants. Device Configuration External Loop Filter Component Values Nominal Performance Using These Values
FVCSO
(MHz)
M Divider R loop C loop Value 30, 32 30k 1.0F
R post 33k
C post 100pF
NBW Mode2
PLL Loop Bandwidth 110 Hz
Damping Passband Factor Peaking (dB) 2.2 10 0.35 0.02
533.333
1 0
3 kHz
Table 7: External Loop Filter Component Values
Note 1: Recommended values for hitless switching. For PLL Simulator software, go to www.icst.com. Note 2: NBW mode 1 = Narrow Bandwidth, where RIN = 2100 k . NBW mode 0 = Wide Bandwidth, where RIN = 100 k . Note 3: This table does not apply to the 400 MHz VCSO option since the Kvco value is different.
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M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
Product Data Sheet
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter Rating Unit
VI VO VCC TS
Inputs Outputs Power Supply Voltage Storage Temperature
-0.5 to VCC +0.5 -0.5 to VCC +0.5
4.6
V V V
o
-45 to +100
C
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Table 8: Absolute Maximum Ratings
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter Min 3.135 Typ 3.3 Max 3.465 Unit
VCC TA
Positive Supply Voltage Ambient Operating Temperature
V
oC oC
Commercial Industrial
0 -40
+70 +85
ELECTRICAL SPECIFICATIONS
DC Characteristics
Symbol Parameter
Table 9: Recommended Conditions of Operation
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = 400-534, LVPECL outputs terminated with 50 to VCC - 2V
Min 3.135
Typ 3.3 175
Max 3.465 225
Unit Conditions
Power Supply VCC ICC Differential Input: LVDS / LVPECL LVCMOS / LVTTL Input Inputs with Pull-down VP-P VCMR VIH VIL IIH IIL IIH IIL Rpullup
Positive Supply Voltage Power Supply Current Peak to Peak Input Voltage 1 Common Mode Input 1 Input High Voltage
REF_SEL, MR_SEL DIF_REF, nDIF_REF
V mA V
0.15 0.5 2
Vcc - 0.85 V Vcc + 0.3 V 1.3 150
Input Low Voltage Input High Current Input Low Current Input High Current Input Low Current Internal Pull-up Resistor
nDIF_REF1, nDIF_REF0 All Inputs FOUT1, nFOUT1 FOUT0, nFOUT0 FIN_SEL1, FIN_SEL0, INIT, MR_SEL DIF_REF1, DIF_REF0
-0.3 -5
51
V A A k
VCC = VIN = 3.456V
Rpulldown Internal Pull-down Resistor Inputs with Pull-up -150
5
51 (Note 2) 4 Vcc - 1.4 Vcc - 2.0 0.4 2.4 LOL , REF_ACK GND
A A k pF
VCC = 3.456V VIN = 0 V
Inputs biased to Vcc/2 2 All Inputs CIN Input Capacitance Differential Outputs VOH VOL VP-P LVCMOS Outputs VOH VOL Output High Voltage Output Low Voltage Output High Voltage, Lock Output Low Voltage, Lock
Vcc - 1.0 V Vcc - 1.7 V 0.85
Peak to Peak Output Voltage 3
V V V IOH= 1mA IOL= 1mA
VCC
0.4
Note 1: Single-ended measurement. See Figure 7, Differential Input Level on pg. 10. Note 2: Biased to Vcc/2, with 50k to Vcc and 50k to ground. Note 3: Single-ended measurement. See Figure 6, Input and Output Rise and Fall Time on pg. 10.
Table 10: DC Characteristics
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M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
Product Data Sheet
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = 400-534, LVPECL outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min DIF_REF1, nDIF_REF1, DIF_REF0, nDIF_REF0 FOUT1, nFOUT1, FOUT0, nFOUT0 Commercial Industrial
M2040-xx-400.0000 M2040-xx-533.3334
Typ
Max 285 534
Unit Conditions
FIN FOUT APR KVCO PLL Loop Constants 1 RIN
Input Frequency Output Frequency VCSO Pull-Range VCO Gain Internal Loop Resistor
200 200
MHz MHz ppm ppm kHz/V kHz/V k k kHz dBc/Hz dBc/Hz dBc/Hz ps ps % % ps ps ps ps ms
20% to 80% 20% to 80%
120 50
200 150
1600 800 100 2100 700
NBW = 0 NBW = 1
BWVCSO VCSO Bandwidth n Phase Noise and Jitter J(t) odc Single Side Band Phase Noise @622.08MHz Jitter (rms) Output Duty Cycle Output Rise Time for FOUT1, nFOUT1,
FOUT0, nFOUT0
2
1kHz Offset 10kHz Offset 100kHz Offset 12kHz to 20MHz 50kHz to 80MHz
FOUT =200-285MHz P = 2 (P_SEL = 1) FOUT= 400-534MHz P = 1 (P_SEL = 0) 2 FOUT =200-285MHz P = 2 (P_SEL = 1) FOUT= 400-534MHz P = 1 (P_SEL = 0) FOUT =200-285MHz P = 2 (P_SEL = 1) FOUT= 400-534MHz P = 1 (P_SEL = 0)
-72 -94 -123
0.25 0.25 45 40 325 200 325 200 50 50 425 275 425 275 0.5 0.5 55 60 500 350 500 350 100
tR
tF tLOCK
Output Fall Time 2 for FOUT1, nFOUT1,
FOUT0, nFOUT0
PLL Lock Time
Note 1: Parameters needed for PLL Simulator software; see Table 7, External Loop Filter Component Values, on pg. 7. Note 2: See Parameter Measurement Information on pg. 10.
Table 11: AC Characteristics
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M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
Product Data Sheet
PARAMETER MEASUREMENT INFORMATION
Input and Output Rise and Fall Time
80% Clock Inputs 20% and Outputs 80% VP-P tR 20% tF FOUT odc = tPW tPERIOD tPW (Output Pulse Width)
Output Duty Cycle
nFOUT
Figure 6: Input and Output Rise and Fall Time
Differential Input Level
VCC - 0.85 nDIF_CLK VP-P DIF_CLK + 0.5 Cross Points VCMR
Figure 8: Output Duty Cycle tPERIOD
Figure 7: Differential Input Level
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Integrated Circuit Systems, Inc.
M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
Product Data Sheet
DEVICE PACKAGE - 9 x 9mm SMT CERAMIC
Mechanical Dimensions:
Refer to the M2040 product web page at www.icst.com/products/summary/M2040.htm for links to recommended PCB footprint, solder mask, furnace profile, and related information.
Figure 9: Device Package - 9 x 9mm SMT Ceramic
M2040 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
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Integrated Circuit Systems, Inc.
Product Data Sheet
M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
ORDERING INFORMATION
Part Number:
M2040- 01 - xxx.xxxx
Temperature " - " = 0 to +70 oC (commercial) I = - 40 to +85 oC (industrial) Frequency (MHz) Consult ICS for available VCSO frequencies
Figure 10: Ordering Information Example Part Numbers
VCSO Freq
(MHz)
Temperature
Part Number M2040-01 - 400.0000 M2040-01I 400.0000 M2040-01 - 533.3334 M2040-01I 533.3334
Table 12: Example Part Numbers
400.0000 533.3334
commercial industrial commercial industrial
Consult ICS for the availability of other VCSO frequencies.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M2040 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
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